library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
-------------------------------------------------------------------
entity Memory_Controller is
    port(Clk,Ld_MAR,Ld_MDR,MIO_EN: in bit; R_W,Mem_En,Data_Size,GateMDR_Cntrl: in bit;
         Bus_in: in unsigned(15 downto 0);
         GateMDR_Val,MAR_temp,MDR_temp,Mem_temp,MDRin_temp: out unsigned(15 downto 0));         
end entity Memory_Controller;
-------------------------------------------------------------------
architecture build of Memory_Controller is
component Memory is
    port(CS, WE0, WE1: in bit; Clk: bit;
         MAR,MDR_out: in unsigned(15 downto 0);
         Ready: out bit; 
         Mem_out: out unsigned(15 downto 0));
end component;
component Logic_GateMDR is
    port(Data_Size: in bit; -- word/byte
        MAR_out,MDR: in unsigned(15 downto 0);
        GateMDR: out unsigned(15 downto 0));
end component;
component Logic_LDMDR is
    port(Data_Size: in bit; -- word/byte
        MAR_out,Bus_in: in unsigned(15 downto 0);
        LogicLDMDR_out: out unsigned(15 downto 0));
end component;
component MIOMUX_logic is
    port(MIO_EN: in bit;
         LogicLDMDR_out,Mem_out: in unsigned(15 downto 0);
         MDR_in: out unsigned(15 downto 0));
end component;
component WE_Logic is
    port(R_W, Data_Size: in  bit;
         MAR_out: in unsigned(15 downto 0);
         WE0, WE1: out bit);
end component;
component MAR is
   port(Clk,LD_MAR: in  bit;
         Bus_in:    in  unsigned(15 downto 0);
         MAR_out:    out unsigned(15 downto 0));
end component;
component MDR is
   port(Clk,LD_MDR: in  bit;
         MDR_in: in  unsigned(15 downto 0);
         MDR_out: out unsigned(15 downto 0));
end component;   
    ---
--signal MIO_En: bit;
signal we_0,we_1: bit;
signal Ready: bit;
--signal Ld_MAR,Ld_MDR: bit;
signal MAR_out,MDR_out,Mem_out: unsigned(15 downto 0);
--signal Mem_out: unsigned(15 downto 0);
signal LogicLDMDR_Val: unsigned(15 downto 0);
signal MDR_in: unsigned(15 downto 0);

begin
  --process(GateMDR_Cntrl)
  --begin             
--Bus_in <= GateMDR_Val when GateMDR_Cntrl = '1'
  --       else "ZZZZZZZZZZZZZZZZ";
    MAR_temp <= MAR_out;
    MDR_temp <= MDR_out;
    Mem_temp <= Mem_out;
    MDRin_temp <= MDR_in;
  --end process;

    MEM: Memory port map(Mem_En,WE_0,WE_1,Clk,MAR_out,MDR_out,Ready,Mem_out);
    LGM: Logic_GateMDR port map(Data_Size,MAR_out,MDR_out,GateMDR_Val);
    LLM: Logic_LDMDR port map(Data_Size,MAR_out,Bus_in,LogicLDMDR_Val);
    MML: MIOMUX_logic port map(MIO_En,LogicLDMDR_Val,Mem_out,MDR_in);
    WEL: WE_Logic port map(R_W,Data_Size,MAR_out,we_0,we_1);
    MAX: MAR port map(Clk,Ld_MAR,Bus_in,MAR_out);
    MDX: MDR port map(Clk,Ld_MDR,MDR_in,MDR_out);
        
end build;